How Intel Took EMIB From Science Fiction to High Volume: Intel Foundry's Ravi Mahajan

0:00 Welcome listeners to another episode of Semi-Doped. I'm Austin Lyons with Chipstrat, and with me is a special guest. We're talking with Ravi Mahajan today. He is a distinguished engineer and the director of the technology and pathfinding group in the advanced packaging, technology, and manufacturing division at Intel Foundry.

0:20 So, Ravi, thank you so much for coming on to talk with us.

0:23 Austin, thank you for inviting me. It's a real pleasure. I really appreciate you taking the time and inviting me.

0:34 Yes, awesome. Great. So we are going to talk a lot about e-mib today, which I'm super excited about because I think most people are fairly familiar with e-mib today, but they've probably only heard about it in the last year or two. And I know that you've been working with e-mib and on e-mib since way back in like 2000 or seven or something.

0:53 So I kind of want to go back to the beginning and trace Intel's history with e-mib, what problem you're trying to solve, and why you came up with EMIB and just kind of work all the way through so that people can get a nice appreciation of EMIB and how it's interesting and everything. But maybe first uh to start us off, like tell us more about you.

1:15 You have a nice long title, and I know you've been at Intel for a long time. So explain more to us, like what you do day in and day out.

1:22 Okay. So I've been at Intel for 34 and a half years. And I joined studying reliability of packages, then I led the thermal group. And for the longest time I helped figure out how to cool parts. I still dabble in that area. And just a little bit of history. You know, today uh laptops are cooled by heat pipes.

1:44 When I started work, the max power dissipated was four and a half watts, and there were no laptops. Today we easily cool more than a kilowatt, and heat pipes are normal. Everybody accepts them as you know a feature. My point is uh I've been working on cooling devices for a very, very long time, and that's what got me my start in the industry.

2:06 Uh in the year 2000, I was asked to lead the pathfinding effort in Intel. Essentially look out in the future and plan so that we have technologies ready, mature, understood, and sort of narrowed down for them to go into production. And I've been doing this ever since. Uh right now I lead the pathfinding group.

2:28 We look roughly three to five years out and get Intel ready for uh what comes in the future. And I do this both as an Intel employee, also as an industry sponsor of a roadmap, the heterogeneous integration roadmap that IEEE Semi and ASME collaborate on.

2:46 Ah, ah, interesting. Okay, tell us just a little bit more about that last, the IEEE group, like like who all participates in, what is the purpose of it?

2:55 So, you know, the it is very evident now that heterogeneous integration, where you take different components that are designed on separate platforms and stitched on a compact packaging platform, but a compact system, uh, bigger picture, is the way compute communications are going to move forward. And you see this everywhere.

3:16 So in the year 2016, when the silicon-driven roadmap, the ITRS, came to an end, quite a few people got together and said, you know, we ought to have a systems-driven roadmap for electronics. If we collectively project a direction that we agree on, then everybody, architects, designers, assembly houses, equipment, materials, all of them, uh, can all converge on a common direction.

3:45 And that way we are ready for the future. So uh IEEE sponsors this primarily. Uh SEMI contributes, uh, and because SEMI is a very good voice in the industry, people listen to what they do along with IEEE that offers technical heft. Uh, and then ASME, the American Society of Mechanical Engineers, also contribute.

4:06 Uh, we also are building connections with other groups, for instance, GEA. And we are collectively writing a roadmap for the future. It is non-confidential, it is strategic, and it is essentially driven by volunteers. You know, lots of technologists from across academia industry come together. And because it's non-competitive, it's a very good venue for people to talk about how we define our futures.

4:33 Nice, awesome. Okay, that that's that's cool because I think that puts, we're going to talk about e-mib in even a bigger perspective, which is the whole industry has to come together to work on these challenges. It's not just one company at a time. And you pointed out it's it's not just the design companies, but it's also the manufacturing and everyone in between, even to the point of materials, which is pretty interesting.

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6:42 Let's go all the way back 2007, I believe roughly around then, and you know, you can correct me if I'm wrong. Um, you published a paper and eMib was uh becoming a thing all the way back then. So maybe explain to listeners what EMIB even stands for, and then take us way back and help help me understand what problems you were trying to solve back then and how you e-mib came about.

7:03 Yeah. So the acronym stands for embedded multi-dye interconnect bridge. It originally started out. I called it a silicon patch when I started a long time ago. A little bit of history, it goes beyond before 2007. Uh we in Intel like to synchronize technology development so that we are ready to jump into manufacturing, uh, high-volume manufacturing together.

7:29 So silicon packaging and system interfaces all have to move in lockstep. Uh the best way to do a roadmap is to align milestones. And you know, in those days, we agreed that we should align to the silicon node milestones, which means when 90 nanometers is ready, the packaging associated with 90 nanometers is ready.

7:50 Same story with 65, 45, 32, 22, etc. So then this brings a natural question. Silicon has a roadmap, you know, the nodes progress at a steady cadence. What attributes on the package should we change to progress at that cadence? That was the question. And there's many things you can do. You know, packages gen over gen cool better, deliver power better, they become thinner, right?

8:15 If you remember in that uh time frame in the early 2000s, laptops were becoming very popular. Everybody wanted thinner, lighter laptops, cell phones, all that kind of stuff. The one area I will focus on in this discussion is interconnects. We two C4 interconnects, which essentially means you take bumps on a die and connect it to pads on a package.

8:38 Those pads are connected to wires that escape through the edge of the die. So you have two natural attributes. The number of bumps per unit area. For some reason, you know, people call them IO, so I'll also call it IO. Bumps per millimeter square or IO per millimeter square. And the other attribute that I was interested in was number of wires that escape the edge of the die, Io per millimeter.

9:02 And because a package is multiple layers, you have to normalize it. So you do Io per millimeter of die edge per layer of the package, right? So think of the number wires that escape the edge of the die. So to start creating a roadmap, you have to look at your history and then project the future. So I went back all the way to the 90 nanometer node and I started just calculating and plotting how many wires escape the edge of the die.

9:29 Uh and you know, I created a plot. It's pretty interesting. It turns out that generation over generation, we were getting 10% better, roughly. And I it's very nice to see something fit on a plot. And when you look at it at a plot, you wonder why it is 10%? Why not 5%? Why not 20%? So that sparked some intellectual curiosity.

9:51 Uh so I asked myself, why not more? What happens if you do more? Uh, and then I realized that in organic packages you print using certain lithographic techniques. Uh silicon, you can print much finer wires. So if there was a way by which you could do silicon wires instead of package wires, or do silicon and package wires, perhaps you have a path to increase IO density.

10:18 So that's one vector, you know, that was one chain of thought, I guess, or one train of thought. The second thing was uh as you try and integrate heterogeneous components, you want to stitch them on a package, and uh you also want to reduce your dye size so you get the benefit of cost, you know, the yield gets better as dye size shrinks.

10:41 So there's quite a few people who wanted to disaggregate dye and stitch them together. And my first the first people who came top to me were the FPGA guys, because the FPGA guys oftentimes take all kinds of interesting devices and stitch it on a package. And they want low power, high density interconnects in quite a few cases.

11:01 So this whole idea of disaggregation also was in parallel or simultaneously evolving. Uh in 2007, there was somebody who came to visit us, an architect, and he asked us if we could split the die into smaller parts and stitch them. He was asking us for what is today called fan out wafer level packaging.

11:25 So I showed him my idea and he liked it. He said great idea, but you know, he realized it was really far-fetched. It was almost science fiction in those days. So I presented it to him, and then I walked out of that room thinking, you know, it's not a bad idea. I should do something with it. So I should highlight two important people in this uh Bob Sanckman, former Intel fellow, uh, and one of the smartest people I've worked with in packaging.

11:51 And then Divendra Malik, who was a colleague of mine, also among the smartest people, all three of us were thinking along these lines. So I go to Divendra Malik and I showed him this idea. And he says, you know, not a bad idea, you should file a patent for it. So then I said, I'm taking a piece of silicon, putting it in an organic package.

12:08 The expansion dismatch is quite high. What happens if it cracks? So I went to another person, Sandeep Sane, and he said, Why don't you cushion it? Why don't you put a soft pad underneath it so that it is decoupled from the package? And that was a pretty good idea. Uh so Sandeep and I wrote the first patent for emit.

12:29 It was like an open cavity bridge, and we said, Why don't we create cavities, put silicon in it, cushion it with a pad, and then attach dye on top. Because we get fine wires, perhaps we make the pitch finer, so you get a lot more internet. And you only get you this by this idea, you get interconnect only where you need it.

12:49 So you don't take the entire area and make interconnects, which is a difference from the silicon interposer. So you have localized interconnects only when you need it, and that was the genesis of this idea. You know, a few people who I talked to and I submitted this patent, and the rest, as I can, as you can know, is history.

13:07 Now everybody's picked this idea up.

13:10 Yeah, yeah, awesome. Okay, this is amazing. So I'm gonna reflect this back and unpack a little bit. So, so back then in kind of the early 2000s, um you were both asking how can we increase Io per millimeter squared, like Io density. Um, and at the same time, the industry and and other people were asking, like, how can we disaggregate from these monolithic chips and actually go toward as people know of them as like chiplets and all the benefits that chiplets entails?

13:41 But of course, to do that, you'll you need to be able to, you know, quote unquote, stitch together these dye. And so it's kind of simultaneously, you're thinking about the packaging, and people are asking and have a need for it. And tell me, at the time then, what was the like the sort of default way to stitch it together to use an organic stuff substrate?

14:01unknown Yeah.

14:02 Yeah. So two things are sorry, uh two things are one is IO per millimeter squared, which is the pitch which you scale down, and then IO per millimeter, which is the wires that you scale. So both of them were important. One is lateral, the other is vertical. Uh and and the default was organic. And uh even then the pitches we were going after were pretty straight-of-the-art.

14:25 I mean, very, very uh, very, very uh challenging to do as is. And EMIB added another layer of complexity to this business.

14:34 Yes, yes, got it. So what ultimately drove you to look to silicon instead of what was it just it was going to be hard enough with organic as is, and silicon was a clever way to let you design even tighter pitches? Or or why did you first reach for this the silicon bridge idea?

14:54 What attracted me about the silicon bridge idea was you do localized interconnects, which means you know not all parts of the dye need to be fine pitch. And in fact, fine pitch wires are not a great idea to deliver power. So there have to be large portions of the dye that use thick wires or fat wires, and then local areas that use fine wires.

15:15 So you decouple high-speed IO from power. And so I thought, why not kill two birds with the same stone? Sort of develop something that's localized for IO and then leave the rest of it untouched.

15:26 Ah, okay, okay. So keep the big, fat, cheap wires for delivering power, and then use the fine pitch, probably expensive, but you could get them small and densely packed together for the high-speed I.O. Yeah.

15:41 And then the expensive part you can get away with by doing just small patches, right? So it's really easy to build a wafer and take small strips out of it. You get a lot of those strips. So the cost is mitigated by doing a bridge.

15:56 Uh, yes, yes. Okay. So you came up with this idea, filed a patent. Um, it was kind of complicated, but you had help um in coming up with ways to think about you know, decoupling it from the substrate and dealing with maybe like thermal mismatch and and other complexities. How did you go from what was the story in going from a patent to actually building it to eventually you know manufacturing it at scale?

16:25 Yeah, yeah, that's a good question. You know, when first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that, right? And then there have there were many enabling technologies that had to come along.

16:47 So I'll list them one by one. Uh the idea said we need four thick metal layers, two microns thick on a silicon process. Typical silicon processes do one or two. I wanted four. So we had to develop a passive silicon process that stacked four thick metal layers. We had to figure out a way to thin and handle these dye.

17:09 And to continue my story about the bridge, you know, Intel had invested in embedding around the same time. We had something called bumpless buildup layers where we were building layers out, and we were learning how to embed stuff. So somewhere along the way, we said, you know, it'd be pretty smart if we embed the dye as well, uh, like these thin stretch.

17:28 So that says you have to learn the embedding process, place them precisely. And we are talking about approximately 5,000 bumps in a very, very tiny area, very fine pitch. So that embedding has to happen. Then you have to create a joint where you put fine pitch bumps with small amounts of solder adjacent to coarse pitch bumps with a lot of solder.

17:50 So imagine trying to squish all of them together, and all of them have to form a joint. So you have to control the solder, you have to control the attached process of thermocompression bonding. That had to come along. And if you do fine-pitch wiring on silicon and you send signals along, you have to boost them every 500 micron-ish with active silicon.

18:11 But here we are talking about a six millimeter long wire with no ability to boost. Right? So you had to design it so that the signal integrity was retained. That was another thing we had to work on. So quite a few of these things had to come along. The equipment, the process, the materials for the dietch film, all that had to come along.

18:28 And that, you know, that was maturing in parallel for different applications. We lined it up for our application. And around 2011, 12, when it was obvious that this was a very good solution and needed for cost and performance, uh, we started building parts. And in 2012 was the turning point. You know, people realized, hey, there's real value here.

18:52 Let's figure out how to build this.

18:54 That sounds complicated. You had to figure out how to make these tiny little bridges, how to embed them, how to put bumps on them and eventually connect them, uh, probably get the alignment just perfect. You had to think about signal integrity. Uh, and and it sounds like lots of sort of industry innovations were happening in parallel, even from like a tooling and equipment perspective, to make this possible.

19:18 And you you mentioned like around you know 2012 or so. Is that did it take you know four or five years just to get to a point where you're like, oh, we can manufacture this? But or or is that when you actually started like, was that just, hey, we made this in the lab and it works? Or is that like, hey, we think we can take this to high volume manufacturing?

19:36 So 2012 was the year in which we started taking it from PowerPoint into actual lab labs, you know. Uh got it. And then 2012-2013 were the years where we got everything together: the equipment, the process, the materials, the design. Uh I should point out one more thing. Uh, chiplets use standardized interfaces.

19:59 So we had to design the pump patterns and the wires to uh conform to a standardized link. You know, in those days, AIB was the link. And today it's UCIE that superseded AIB. So we had to design it so that it met AIB requirements, and today we design it to meet UCIE. So there was a design component to this whole thing.

20:20 Ah, yes. Yes, yes. So then how did it go then? Like when did it finally make its way into you know high-volume manufacturing? And what was like the first use case? Was it the FPGAs or was it HBM? I feel like I read about that somewhere.

20:35 It was the first use case. There were two parallel use cases. There was an FPGA with HBM use case, and there was a graphics chip Intel was designing that also used HBM. Uh the year 2013 was spent really understanding the nuances of manufacturing. 2014 was when we were convinced now that we could build enough to tell us how to scale it in HBM.

20:59 So middle of 2014, Intel announced this, August 2014, if I'm not mistaken. We announced to the world that we have this technology and we know what it takes to make it, and then uh then we started putting in infrastructure to ramp it.

21:13 Got it. So you were almost like a decade in and thinking about it until the point where you actually announced it.

21:21 Yeah.

21:22 Yeah, yeah. Which I think just goes to show that it's complicated. And uh it also makes me think, oh, I wonder what you're working on now that you're gonna announce, you know, seven years from now or five years from now.

21:36 But I can have to point out one more nuance, Austin. It's important to recognize. Yes, yes, solder volumes, right? So large solder and tiny solder. Now, tiny solder volumes have a problem with electromigration, as in you don't just have enough. So you have to first squish them and then you heat them over and over again, they uh electromigrate.

21:54 Like I mean, you form intermetallics, they become hard. So we solve that problem as well by. Containing and designing the volume of solder for those pitches, which I think is a techno technological marvel.

22:06 Amazing. Which how how many people were working on this at that time, would you say?

22:13 Uh my original team was seven people in 2013. It expanded to about 150 to 220 uh 2014 by the first half of 2014. And then we had multiple uh groups of people who came in to work, you know, suppliers, us all of them.

22:33 Sure, sure, yeah, totally. Yes, because it sounds very cross-disciplinary. Um, so why was HBM like a first application that needed eMib, needed these local silicon bridges embedded for the fine pitch and everything?

22:51 Uh so there were, if you go back to that time, there was three three application spaces that really would have loved to have fine-pitch interconnect. One was FPGA, because they do all kinds of heterogeneous drive, and they wanted HBM to give them local memory. And the value of HBM is you get high bandwidth interconnects and you also get high capacity DRAMs in parallel.

23:15 Uh, and it is designed to be a low-power, like high-energy efficiency bus. Uh, there was a competing technology called wide IO2. The mobile application also wanted local DRAMs, and they were focused on optimizing wide IO2 for mobile. And then the GPU applications wanted HBN because they wanted to put a bunch of HBMs next to the computer.

23:39 You see those designs today. Yeah. So they wanted access to a lot of memory, you know, high bandwidth, low power. Uh so there were three competing markets, and we did our math internally, and we figured that if you get the highest performing designs, then you can waterfall everything down. And that's why we picked HBM.

24:00 Ah, got it. So HBM would be the most sort of demanding use case, and if you can make EMIB work for that, then it'll work for everything else.

24:09 Yeah. Uh we had to pick the memory, and you know, HBM, you have to attach many HBMs. Um, like, you know, we we started with four, and I think we just scaled up over time.

24:20 Yes, yes, totally. Um, okay, so so this is a fascinating history from the idea all the way through the the early applications. Um, now I think is a good time to jump into talking about TSMC's co-s, which is or just co-ops in general, which is a way to package and interconnect dyes and help the listener understand.

24:47 Because I think a lot of people have heard about, generally they hear about um co-as is a bottleneck, there's not enough co-as capacity, so on and so forth. Um, help people understand, you know, uh maybe some differences or similarities between co-as and eMib.

25:01 So uh let me first describe coas in very simple terms. Uh the idea is that you take a silicon interposer with similar pitches and similar wiring densities as EMI. Uh so think of it as a, let's say you have a rectangle and you put multiple dye on top of it. Now the total dye area that you can put on that rectangle has to be smaller than the size of the rectangle.

25:27 So if you want more and more dye, you have to increase the size of the base. And so what happens is it's a great technology, uh, but what happens is as you increase the size of the base, you get fewer and fewer dye out of a wafer. So in today's AIHPC world where people want a lot of interconnects, they want a large co-s.

25:51 That's why you hear terms like 2x reticle, 4x reticle. Uh so the size increases. So that's one thing. Uh it's a great technology, but it has this particular scaling concern. The second thing is you connect a die and you send a signal through through silicon bias in the interposer and then they connect to the package.

26:11 The pitch of the interposer to package has also to be carefully designed for reliability. That's the other thing. Also, you're adding an extra length in signaling through this. The third thing is you uh compel the dye pitches to uh be roughly uniform and every aspect of the dye to have to deal with fine pitch interconnects underneath, uh, you know, not just in the IO regions.

26:41 EMIB, on the other hand, has got much lesser silicon area. So you can get many bridges. You can decouple your silicon manufacturing process for the bridge and the embedding process from the attached process, if you will. Like, you know, imagine you make a bunch of bridges, you slice the wafer, thin them, slice the wafer, send it to a substrate manufacturing line to embed in there.

27:05 Whatever losses you take, don't get engaged, don't get compounded with the loss of the assembly at the end. There is no size or scaling limitation because you're not you're not worried about the size of the base, if you will. Also, you're no longer restricted by the size of the base. You can put more and more.

27:26 That's why you see packages with 16, 20-ish bridges, and the size of the package is pretty large. Uh, eMIP is easily scalable to a panel scale process. So, you know, you can imagine a panel with larger and larger packages with more and more bridges. Uh, so it's uh the way I look at it is interconnections where you need them and only where you need them.

27:49 Okay, okay. Yeah, yeah, yes, yes. Let me reflect it back. So when I think about uh co-op style, I'm thinking about an interposer that ultimately it's like there's a substrate is the base layer, and then I've got this interposer layer, and then I put the die on top, and the connections go from the die through the interposer over to the other die.

28:12 And your first point was that when I want to design a system, let's say maybe with uh two GPUs on it or four GPUs on it, plus HBM for everything, that's going to grow geometrically. It's gonna be bigger in area because I'll be all these reticle-sized compute dies, plus a bunch of maybe HBM and I/O and whatnot.

28:34 And that requires the interposer itself to continue to get bigger and bigger that they sit on and connect. And so to your point, was when I'm creating that interposer, the wafer that it's coming from, obviously, that interposer itself is taking up more and more of the wafer that it comes from. Um, as opposed to eMib, where the little silicon bridges are, you know, made and diced separately.

29:02 And then the substrate, instead of attaching, instead of an attached step where you're attaching an interposer and kind of attaching the die on top of that, for eMib, it's an embed step where you've got the substrate and you need to just take these tiny little dye, which is not trivial to do, but you take the little bridges and you embed them in the right place.

29:22 And then you're ultimately putting the die right on top of that substrate. So instead of like three layers tall, it's two layers tall with the silicon bridges embedded. And then to your point, this can scale to you know, however large is needed, because again, then at that point it's just about the substrate scaling and properly embedding the little bridges.

29:44 And so, for example, maybe the substrate's even a big panel or something. Um, but it's it just inherently you're because you're taking little bridges and putting them where you need them, that sort of scales indefinitely, if you will.

29:57 Yeah, yeah. I mean that it's localized interconnect bridges where you need them and you know standardized interconnect. So you have standardized bridges though.

30:06 Yep, yep, that makes sense. Um, and so the how how should we think about yield in terms of eMib? Is when when people talk about e-mib's yield, is it it feels like just taking silicon and dicing up and getting lots of little bridges, that doesn't seem the hard part where there would be yield concern. Is are is the tricky part actually the embedding step?

30:28 Yeah. That's what took the most of our energy to figure out a way by which you embed them and get the yield up. So you know, get the right class of equipment to do the embedding right. And then once you have a substrate with an embedded or multiple embedded bridges, how do you do the attach where you have coarse pitch attach in the central regions and localized fine pitch attach at the edges?

30:55 And that's where you know I'm really proud of the team that worked on it because these guys developed models, they figured out how to get all of this down to a T, how to embed, how to attach, how to manage the process, control the attached process. That's like a really fascinating engineering exercise.

31:15 Yeah, yeah, very impressive. Well, what fun work for people who work at Intel Foundry to work on, too. Those are good challenges. So eMib is very fascinating, and we're talking about it in terms of like AI accelerators, for example, because I think that's what everyone can relate to today. Are there other use cases for eMib?

31:34 I mean, ultimately, will everything be um, you know, using chiplets and needing e-mib?

31:43 Uh everything would use chiplets, not all of them will need eMib. So if you take UCIE as an example case, UCIE has two forms. There is UCIES, which is standard organic packages, you know, nothing special needed in terms of bridges or others. And there is UCIEA. So the idea of chiplets uh goes past the idea of EMIB itself, but eMib is an important enabler for chiplets.

32:11 And the other thing is uh COWAS can enable chiplets just as well. You can design you know chiplets in both of them. Uh and just like you use bridges only where you need it need them, you use COAS when you need it. So you have now like a you know, you have a pretty good uh set of options, like a portfolio that you can pick and choose from.

32:33 Got it, got it. Um, so now I know there's now in the last couple years there's been newer versions of flavors of eMib, so to speak, uh eMib T and EMIB M. What are those and why was like the original e-mib not enough?

32:50 Uh actually, the original e-mib uh the in the patent had everything. It had M, it had T, all flavors.

32:57 Oh, okay.

32:58 Yeah. We uh but when we started building it, we thought it was easier to develop a technology complex as it was uh without the through silicon VS. Now what happened, what happens in that bridge is you have to wrap around the bridge to deliver power. So power delivery is a bit tortuous, but it's you know not that big a deal, but it is torturous in design.

33:19 Uh, if instead of wrapping around power, wrapping around the bridge, if you deliver power straight up, which is what EMIPT does, you have an advantage. You know, you you can do multiple power rails and you can control voltage and eventually you can control power. Uh embedding the MIMP cap technology, which is essentially capacitors and uh metal layers, is something that we have had for a very long time.

33:44 So it seems like a natural thing to add it to the bridge as well, and offer local improvements in power delivery performance, you know, like a uh uh local capacitance for local sort of uh voltage route management. So that's a natural natural version of EMIB as well. Got it, got it. There's one more version I should point out, Austin.

34:06 Sorry to interrupt, but yeah, yeah. You know, why does the EMIB have to be passive? Why can it not be active as well? So, and we published a paper last year where we showed that if you if you put simple repeater circuits, you can even boost a signal as it goes through the length of the bridge. So that's another variant that we can work on.

34:27 Ah, what what's the use case there? Is it really big chips or something? SoCs?

34:34 Well, there were two or three use cases. You know, architects always get interested when they see ideas like this. They wanted to distribute IP. Somebody wanted to send it over longer lengths. And I I felt that if we have the core technology enabled, we can show what it is capable of, and then architects can use it the way they want.

34:54 Sure, sure. So eMib T through silicon vias and e-mib M with the MIM uh capacitors, uh metal insulator metal capacitors, and and this sort of active e-mib, all of these are really just tools that the foundry is giving to the designer to help them better manage power delivery and maybe do other innovative things.

35:18 Yeah. Yeah. At different levels of maturity, obviously. The EMIPT will take a lot more work, but the existence proof is there. So we published it last year to show what you can do if you had an active, the how to do an active route.

35:31 Got it. Nice. Um, okay. So now I know that Intel Foundry, obviously, the last several years have been very interesting for Intel and for Intel Foundry and for us, you know, ecosystem uh watchers, with uh Foundry taking on more and more of a focus on external customers and not just being uh a captive Foundry for an IDM.

35:53 Um, and I know that uh Intel Foundry has said quite often, um, hey, we will package dyes from any foundry. So you don't you could use Intel Foundry for packaging, but you don't necessarily have to use it for your logic die. Of course, you can if you want, but but Intel Foundry is willing to package dyes from anyone else.

36:12 Um, so I'm curious, as that relates to eMib, uh, it is that like harder for any reason, or is it not conceptually just it doesn't matter where the die comes from, the technology is the same?

36:26 It's not harder necessarily, conceptually very similar. You just have to make sure that the specs of the die that comes in for packaging meet what you require for your assembly process. Sure. Conceptually, not much harder. Yeah, just different. That's it.

36:43unknown Yep.

36:43 Yep, yep, yep. That makes sense. Um, and so then maybe relatedly, as I'm thinking about Intel taking dyes from other people, if alternatively, do other like OSATs or anyone have the ability to do e-mib, or is that an Intel Foundry only technology?

37:01 Yeah, Intel Foundry is the only foundry packaging EMIP today. And we have really we have a pretty robust ecosystem that enables this packaging for with EMIP.

37:11 Okay, yep. Makes sense. Um, okay, so maybe catch us up on the uh we talked very early on about your role in the broader industry with the heterogeneous integration roadmap. Um as you're sitting in that position and you know, just being a pathfinding person, always looking ahead. Like what is the industry's biggest packaging gap, you know, looking forward beyond EMIB?

37:38 So the way we did this roadmap was to have a systems focus and ask what kind of systems are going to be built. And we really expanded the envelope to many, many things. Uh, for instance, medical devices, manufacturing in space, defense, devices that are used in aircrafts, defense, uh, you know, all kinds of stuff, uh, laptop or mobile devices.

38:02 Then we said, how do we develop technologies that meet the requirements of these different segments? Some of them have, you know, they put more pressure on size, some of them have to deal with much higher power, some of them have to deal with higher densities. Uh so we tried to distill out common elements.

38:24 Then we said, you look at advanced interconnect technologies, push the interconnect envelope and let it waterfall in these segments. Uh the areas that we all have to focus on is how do you deliver power more efficiently so that the bulk of the power that goes from, say, the wall to the device is used for what the device does and is not lost along the way.

38:45 So efficiency has to be improved. That's a big deal, especially now that we are talking about high-powered devices, right? So you don't want to lose power along the way. You have to be able to cool. And cooling is always an interesting challenge because you have to understand the demand function. You know, how much power, how dense is the power, where is it, what are the temperature limits you need to deal with.

39:08 So cooling across the board is a very important and interesting challenge that we need to focus on. Power delivery, cooling is then manufacturability. We are talking about stitching multiple devices in a complex composite, which is you know, silicon, metal, organic, all together. So you have to be able to forecast what its stress rate is going to be and design it so that it stays reliable.

39:33 You have to find the right equipment, understand the precision of placing and how to design the equipment. What materials do you have? What materials do you need to develop? And materials take a long time before you can integrate them. So you have to anticipate some of this. And in addition to materials, the interfaces of these materials are just as important.

39:54 You know, so you focus on that. Uh, then do you have the design tools? How does this play into the EDA world? You know, there's physical design, and then there is the thermomechanical and electrical design. So they all have to play together. So there is that thing as well. So there's like a host of things.

40:09 Uh, we wrote a paper in Nature earlier this year, in Nature uh electronics reviews uh that sort of starts to show this to the rest of the world on what the complexity is and what you need to do to figure out how to get ahead of the game plan.

40:25 Yeah, amazing. It it does sound so again, multidisciplinary and complex. Obviously, packaging is no longer just about electrical, it's obviously electrical, thermal. You talk about power, you talk about materials, material interfaces, um, even EDA, of course, uh being able to simulate all of this. Um, I guess, you know, maybe on that topic, last question.

40:51 You know, recently I talked to Synopsis and they're thinking a lot about agentic AI. And you're obviously pathfinding and doing kind of like basic research and thinking further out. But uh is is AI and agents coming into your workflow or the industry's workflow at all, even at a pathfinding perspective?

41:09 Yeah, yeah, in a couple of ways, Aston. The one is I I also have heard similar talks from synopsis, cadence, semen's, uh, and we we seem to be talking the same language. Um AI can be utilized to pick optimization paths faster. Uh you know, you can uh you can also use it intelligently in manufacturing to distill out yield loss mechanisms and then filter them out of the system.

41:36 So there's a lot of opportunity to use AI to accelerate design and eventually create digital twins in a real sense, you know, predictive uh digital twins that tell you how will a structure, uh, what will be the state of stress of a structure as a function of time, reliability, exposure, and then design something that fits within a reliability envelope.

41:59 So there's a lot of value in many aspects of semiconductor uh packaging for AI to be used.

42:06 Yeah, fascinating, fascinating. Okay, so so far we've been talking about essentially electrical interconnects um at you know very small scale with eBib. And, you know, really 20 Intel has 20 years of history here, which is incredible and amazing. And when you describe how complex it is, like of course it took 20 years because it's very complicated and now it's very robust and in you know in production.

42:33 Um now, a lot of there's a lot of talk in the AI era about other interconnects, uh, optical interconnects, of course, being one. And I know that Intel Foundry has some experience over time with uh, you know, optics, silicon photonics, that kind of thing. Uh is there anything in that realm that you have been working on or your team has been working on that you're able to talk about?

43:00 Yeah, I can uh let me start conceptually first. If you look at what a package does, essentially it has lateral connections on the surface of the package that connect different components and then connections that go through the package to the motherboard, if you will, or the PC. Um what if we could increase the bandwidth capability of the package uh by building complementary optical interconnects?

43:26 So, you know, what if if you could use the top surface of the package to send light in and out? So we uh so that way you look at the package and you say, you know, how much bandwidth do I eke out of it? You get a lot more because you get a lot of bandwidth density. You have to learn how to attach an EIC to a PIC.

43:47 You have to figure out how to integrate the light sources, make sure they're reliable, make sure that the interface between the photonics IC and the system connection is has a scalable path. So I've published quite a bit in this area. Uh and I am convinced that if you do this right, optical will significantly improve the bandwidth you get in and out of a package.

44:11 Uh so we focus mainly on topside optics today. That's what our publications have been. And the ecosystem is maturing quite a bit. You know, Intel has a fab that does photonics ICs. We know how to do attach, and we've demonstrated high-yielding attach in some regions. So we are sort of internally uh maturing quite well.

44:33 Amazing. And ultimately, is that top side, you know, optical attachment optical fibers coming in, bringing, bringing obviously increasing the bandwidth, uh the IO bandwidth significantly there. Um, is that primarily in in die-to-die applications, or is that uh connecting to other chips or to a switch or something?

44:56 Package to package uh is where package to package. It will, you know, we we have near package optics today, and we have transceivers, pluggables. Eventually, and I hope it happens sooner than later, you will have co-packaged optics for power and density reasons, but it'll be package to package. Gotcha.

45:14 Okay, fascinating. Well, you know, I think we'll have to do another conversation sometime where we can go deep into that because it's very interesting, and I'd love to learn more from you on that. Um, but with that, we are at time. So thank you, listeners. I hope you learned a lot. I hope that you have a great appreciation now for Intel's e-mib history and some of the benefits of eMib.

45:34 And Ravi, thank you so much for your time today.

45:37 Oh, my pleasure. Thank you for having me. I appreciate it.

45:40 Anytime.